LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design:   J:\Textes\STI\Terminales\Projet 2007_2008_Pompe péristatique\ELECTRONIQUE\Dossier Prof\ACTIVITE B (FP3-Bulles)\4046\4046_modele.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  14/01/08
Modified: 16/01/08

*PROPERTIES,0    

*MODELDEFS,6    
LX_D_LED : ISAT=1E-14, N=3, RS=2, BV=15.0, CJO=50pF
LX_D_POW : ISAT=10u,RS=1,CJO=20p,TT=50n
LX_D_SCHB : ISAT=100n,RS=12,CJO=1p,TT=5n,EG=0.69
LX_D_SS : ISAT=10n,RS=10,CJO=2p,TT=10n
LX_D_SSG : ISAT=1u,RS=15,CJO=1p,TT=8n,EG=0.67
LX_D_ZEN : ISAT=10n,RS=5,CJO=1p,TT=1n

*PARTLIST,48   
U1_D1,DIODE,,N=100m,PRIMITIVE=ANALOG,TEMP=27
U1_D2,DIODE,,N=100m,PRIMITIVE=ANALOG,TEMP=27
U1_R1,RESISTOR,1.0,PRIMITIVE=PASSIVE
U1_R2,RESISTOR,1E8,PRIMITIVE=PASSIVE
U1_R3,RESISTOR,1E8,PRIMITIVE=PASSIVE
U1_V1,VSOURCE,15-100m,PRIMITIVE=ANALOG
U1_V2,VSOURCE,-15+100m,PRIMITIVE=ANALOG
U1_VCI1,VCISOURCE,100E6/1.0,PRIMITIVE=PASSIVE
U2_D1,DIODE,,N=100m,PRIMITIVE=ANALOG,TEMP=27
U2_D2,DIODE,,N=100m,PRIMITIVE=ANALOG,TEMP=27
U2_R1,RESISTOR,1.0,PRIMITIVE=PASSIVE
U2_R2,RESISTOR,1E8,PRIMITIVE=PASSIVE
U2_R3,RESISTOR,1E8,PRIMITIVE=PASSIVE
U2_V1,VSOURCE,15-100m,PRIMITIVE=ANALOG
U2_V2,VSOURCE,-15+100m,PRIMITIVE=ANALOG
U2_VCI1,VCISOURCE,100E6/1.0,PRIMITIVE=PASSIVE
U3_D1,DIODE,,N=100m,PRIMITIVE=ANALOG,TEMP=27
U3_D2,DIODE,,N=100m,PRIMITIVE=ANALOG,TEMP=27
U3_R1,RESISTOR,1.0,PRIMITIVE=PASSIVE
U3_R2,RESISTOR,1E8,PRIMITIVE=PASSIVE
U3_R3,RESISTOR,1E8,PRIMITIVE=PASSIVE
U3_V1,VSOURCE,15-100m,PRIMITIVE=ANALOG
U3_V2,VSOURCE,-15+100m,PRIMITIVE=ANALOG
U3_VCI1,VCISOURCE,100E6/1.0,PRIMITIVE=PASSIVE
D1,DIODE,DIODE-ZEN,BV=7.3,IBV=2mA,MODEL=LX_D_ZEN,MODFILE=DIODE,PRIMITIVE=ANALOGUE
IR1,ACS,"0.25*I(A,B)",PRIMITIVE=ANALOGUE
IR2,ACS,"0.51*I(A,B)",PRIMITIVE=ANALOGUE
RA,RES,100k,PRIMITIVE=ANALOG,PRIMTYPE=RESISTOR
RB,RES,100k,PRIMITIVE=ANALOG,PRIMTYPE=RESISTOR
RC,RESISTOR,750k,PRIMITIVE=ANALOGUE
RD,RESISTOR,750k,PRIMITIVE=ANALOGUE
S1,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,RON=1k,VH=1,VT=2.5
S2,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S3,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S4,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VT=2.5
S5,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S6,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S7,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S8,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S9,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
S10,VSWITCH,VSWITCH,PRIMITIVE=ANALOGUE,VH=0,VT=2.5
U4,XOR_2,XOR_2,PRIMITIVE=DIGITAL
U5,AND_2,AND_2,PRIMITIVE=DIGITAL
U6,AND_2,AND_2,PRIMITIVE=DIGITAL
U7,DTFF,DTFF,PRIMITIVE=DIGITAL
U8,DTFF,DTFF,PRIMITIVE=DIGITAL
U9,OR_2,OR_2,PRIMITIVE=DIGITAL
U10,INVERTER,INVERTER,PRIMITIVE=DIGITAL

*NETLIST,33   
#00000,4
U7,OP,Q
U5,IP,D0
S5,PS,P
U9,IP,D0

#00001,1
U7,OP,!Q

#00002,2
U7,IP,RESET
U5,OP,Q

#00003,4
U8,OP,Q
U9,IP,D1
S6,PS,P
U6,IP,D1

#00004,1
U8,OP,!Q

#00005,2
U8,IP,RESET
U6,OP,Q

#00006,3
S7,PS,N
S8,PS,P
U10,OP,Q

#00007,3
S9,PS,N
S10,PS,P
U9,OP,Q

#00008,2
U4,OP,Q
U10,IP,D

#00009,2
U1_D1,PS,K
U1_V1,PS,+

#00010,2
U1_D2,PS,A
U1_V2,PS,+

#00011,2
U2_D1,PS,K
U2_V1,PS,+

#00012,2
U2_D2,PS,A
U2_V2,PS,+

#00013,2
U3_D1,PS,K
U3_V1,PS,+

#00014,2
U3_D2,PS,A
U3_V2,PS,+

SIGIN,5
SIGIN,IT
RC,PS,1
U4,IP,D0
U7,IP,CLK
U6,IP,D0

COMPIN,5
COMPIN,IT
RD,PS,1
U4,IP,D1
U8,IP,CLK
U5,IP,D1

INH,2
INH,IT
S4,PS,P

ZENER,2
ZENER,IT
D1,PS,K

PC2OUT,3
PC2OUT,OT
S5,PS,-
S6,PS,+

VCOOUT,3
VCOOUT,OT
S2,PS,-
S3,PS,+

CX1,8,IC=2.5
CX1,IT
S1,PS,+
S1,PS,P
IR2,PS,-
IR1,PS,-
S4,PS,+
S3,PS,P
S2,PS,N

PC1OUT,3
PC1OUT,OT
S7,PS,-
S8,PS,+

VDD,11
VDD,PT
S7,PS,+
S7,PS,P
S5,PS,+
S9,PS,+
S9,PS,P
U7,IP,D
U8,IP,D
S2,PS,+
S2,PS,P
RA,PS,1

PP,3
PP,OT
S9,PS,-
S10,PS,+

#00015,6
U1_VCI1,PS,+
U1_R1,PS,1
U1_D1,PS,A
U1_D2,PS,K
IR2,PS,+
IR2,PS,A

U1_+IP,5
U1_+IP,IT
R2,IT
U1_VCI1,PS,P
U1_R3,PS,1
IR2,PS,B

U1_-IP,5
U1_-IP,IT
U1_VCI1,PS,N
U1_R2,PS,1
RA,PS,2
RB,PS,1

#00016,6
U2_VCI1,PS,+
U2_R1,PS,1
U2_D1,PS,A
U2_D2,PS,K
IR1,PS,+
IR1,PS,A

U2_-IP,4
U2_-IP,IT
VCOIN,IT
U2_VCI1,PS,N
U2_R2,PS,1

U3_+IP,8
U3_+IP,IT
U2_+IP,IT
R1,IT
U3_VCI1,PS,P
U3_R3,PS,1
U2_VCI1,PS,P
U2_R3,PS,1
IR1,PS,B

DEMOD,8
U3_-IP,IT
DEMOD,OT
U3_VCI1,PS,N
U3_R2,PS,1
U3_VCI1,PS,+
U3_R1,PS,1
U3_D1,PS,A
U3_D2,PS,K

GND,40
GND,PT
CX2,IT
VSS,PT
U3_V1,PS,-
U3_V2,PS,-
U3_R3,PS,2
U3_R2,PS,2
U3_VCI1,PS,-
U3_R1,PS,2
U2_V1,PS,-
U2_V2,PS,-
U2_R3,PS,2
U2_R2,PS,2
U2_VCI1,PS,-
U2_R1,PS,2
U1_V1,PS,-
U1_V2,PS,-
U1_R3,PS,2
U1_R2,PS,2
U1_VCI1,PS,-
U1_R1,PS,2
S6,PS,-
S6,PS,N
S10,PS,N
S10,PS,-
S5,PS,N
U7,IP,SET
U8,IP,SET
RD,PS,2
RC,PS,2
S4,PS,-
S4,PS,N
S1,PS,N
S1,PS,-
S3,PS,N
S3,PS,-
S8,PS,N
S8,PS,-
RB,PS,2
D1,PS,A

*GATES,0